1.6T Transceiver · OSFP-XD · 8×200G PAM4
T5-class DSP Rx equalization — watch each lane converge from raw ADC samples to KP4-clean symbols.
aggregate
0.00 Tb/s
lanes locked
0/8
module temp
49.9 °C
DSP
Luma T5
OSFP-XD skeleton · top view
MPO-16 ⇄ LC-8 · CWDM8 · 26.5 dB power budget
click a lane trace above or a row below to inspect its DSP pipeline · tick 0
T5 Rx equalization pipeline
lane λ0 · 1271 nm · pre-FEC BER 2.00e-3 · post-FEC 1.0e-15 · SNR 6.9 dB
KP4 threshold 2.4×10⁻⁴
stage 1
TIA
linear front-end
100% converged
→
stage 2
ADC
7-bit · 106 GSa/s
100% converged
→
stage 3
CTLE
continuous-time EQ
0% converged
→
stage 4
FFE
31-tap feed-fwd
0% converged
→
stage 5
CDR
baud-rate timing
0% converged
→
stage 6
DFE
5-tap decision fbk
0% converged
→
stage 7
MLSE
maximum-likelihood
0% converged
→
stage 8
SLICER
PAM4 → 2b
0% converged
→
stage 9
KP4 FEC
RS(544,514)
0% converged
PAM4 eye · post-DSP
lane λ0
FFE tap weights
31-tap · adaptive LMS
DFE decision feedback
5 post-cursor taps
per-lane telemetry · 8 × 200G
| lane | λ nm | Rx dBm | Tx bias mA | temp °C | SNR dB | pre-FEC | post-FEC | state |
|---|---|---|---|---|---|---|---|---|
| λ0 | 1271 | -2.32 | 63.5 | 51.4 | 6.9 | 2.00e-3 | 1.0e-15 | ◐ training |
| λ1 | 1291 | -3.07 | 64.6 | 50.0 | 6.6 | 2.00e-3 | 1.0e-15 | ◐ training |
| λ2 | 1311 | -3.21 | 66.1 | 51.0 | 7.5 | 2.00e-3 | 1.0e-15 | ◐ training |
| λ3 | 1331 | -2.85 | 63.4 | 52.0 | 6.9 | 2.00e-3 | 1.0e-15 | ◐ training |
| λ4 | 1351 | -2.64 | 65.5 | 48.9 | 6.4 | 2.00e-3 | 1.0e-15 | ◐ training |
| λ5 | 1371 | -2.73 | 63.2 | 48.4 | 7.4 | 2.00e-3 | 1.0e-15 | ◐ training |
| λ6 | 1391 | -2.24 | 67.3 | 49.5 | 7.7 | 2.00e-3 | 1.0e-15 | ◐ training |
| λ7 | 1411 | -2.10 | 62.7 | 48.2 | 6.8 | 2.00e-3 | 1.0e-15 | ◐ training |